1. Field of the Invention
The present invention relates to a method of programming a nonvolatile memory cell and a related memory array, and more particularly, to a method of programming a flash memory cell and related flash memory array.
2. Description of the Prior Art
A prior art technology, which is called an MLC (multilevel cell) technology, is utilized for producing nonvolatile memory cells capable of storing at least two bits, especially for flash memory cells. In a flash memory cell produced from the MLC technology and called an MLC flash memory cell, data stored in the MLC flash memory cell is determined by various threshold voltage levels of the MLC flash memory cell. For example, in an MLC flash memory cell capable of storing two bits, it may take four types of threshold voltage levels for determining the stored data, and when it comes to three bits, it may take eight types of threshold voltage levels, etc. MLC technology enables storage of multiple bits per memory cell by charging the polysilicon floating gate of a transistor to different levels, or by charging the dielectric storing layer of a transistor to different levels, on both of which the structure of the MLC flash memory cell depends. MLC flash memory cells must be able to manage electrical charge precisely, and more specifically, the MLC flash memory cells must be able to place charge with precision, sense charge with precision, and store charge over time. Each MLC flash memory cell is made up of a single transistor, which is directly connected to appropriate control voltages in order to accomplish pinpoint accuracy in charge manipulation.
The abovementioned description is not only for a single MLC flash memory cell, but also for an MLC flash memory array comprising a plurality of MLC flash memory cell aligned in rows and columns. Therefore, the abovementioned description is also available for the MLC flash memory array in the following disclosure.
During programming, in an MLC flash memory array, each MLC flash memory cell through bit-line and word-line connection enables precise charge placement. A control gate of a flash memory cell links to an internally generated supply voltage of the MLC flash memory array through a direct word-line connection and row decoding. The drain of the MLC flash memory cell is pulsed at a constant voltage through a direct bit-line connection and column decoding. The source of the MLC flash memory cell is directly connected to ground. Electron storage on the floating gate of the MLC flash memory cell creates a potential that must be overcome by the control gate. This potential results in a higher turn-on threshold voltage for the MLC flash memory cell, which also is a transistor. Direct, precise gate and drain control is critical to MLC flash memory cell placement.
The MLC technology takes advantages of the multiple program bits in single MLC flash memory cell. When an MLC flash memory cell, or a MLC flash memory array, is applied with an adequate programming method, the MLC flash memory cell may have a well-reacting speed and precision in programming the bits stored in floating gates. There are some available programming methods of the prior art for programming in the MLC flash memory cell or the MLC flash memory array, however, the programming methods have respective benefits and defects corresponding to respective properties. For example, a first programming method is called Fowler-Nordheim tunneling (FN tunneling), a second programming method is called channel-hot-electron injection (CHE injection), and a third programming method is called source-side channel-hot-electron injection (SSI injection).
The FN tunneling is achieved by forcing electrons to or from the floating gate, which is achieved by applying a voltage between a control gate and the substrate of the MLC flash memory cell. By applying different types of voltage levels on the control gate coupled to a corresponding word line, the drain region coupled to a corresponding bit line, and the source region of the MLC flash memory cell, operations of the MLC flash memory cell, which include a write operation, a read operation, and an erase operation, are executed. The FN tunneling allows MLC flash memory cells of an MLC flash memory array to be programmed in parallel, thereby, a total throughput of programmed bits of the MLC flash memory array acquires a high programming efficiency. However, the FN tunneling takes a longer time in cell programming, which is at least 50 μs, caused from changing strong electric fields inside the MLC flash memory cell. Moreover, the programming characteristics about threshold voltage level distributions are not uniform enough because of variations of some related device parameters, for example, a gate-coupling ratio.
The CHE injection is achieved by generating hot electrons and is applied on simple stacked-gate devices. In the method, an MLC flash memory cell is switched on with a high voltage level at the control gate, and an intermediate voltage level at the drain region. Therefore, with the aid of a large electric field formed on a drain junction, electrons are accelerated by the electric field, and the hot electrons are thus generated. In a write operation of the MLC flash memory cell, the hot electrons are dragged with another electric field generated from the control gate to the floating gates. The CHE injection may achieve a high-speed cell programming and a uniform programming, however, the CHE injection has a low programming efficiency caused by the incompatibility between the position of the high vertical electric field and the position where hot-carriers are generated. Generally speaking, a magnitude of programming currents is required to be about or more than 100 μA per cell, and therefore, the number of simultaneously programmed MLC flash memory cells is few because of power limitations provided by internal pumping circuitry.
The SSI injection acquires a fast cell programming and a good programming parallelism. Note that a split gate structure is further applied in the SSI injection, and an additional select gate, which may be a sidewall gate of an MLC flash memory cell, is thus applied. For applying the SSI injection, the select gate has to be operated in a sub-threshold region of the MLC flash memory cell, and a pinch-off point appears at the boundary between the select gate and the floating gate. Since the select gate is utilized for enhancing generated hot electrons, a vertical electric field at the pinch-off point help inject hot electrons into the floating gate. A low channel current is required for applying the SSI injection. Since the select gate has to be operated in a sub-threshold region of the MLC flash memory cell, the channel current, which is denoted as Ids, varies exponentially with linear variation in the threshold voltage level, which is denoted as Vth, of transistors formed under the select gate. If a charge injected into the floating gate is denoted as Qg, then Qg may be expressed as:Qfg=λ×Ids×t  (1)where λ represents a programming rate of the MLC flash memory cell and t represents time. Since variation of the channel current Ids is affected by the threshold voltage Vth of the select gate exponentially, the programming speed λ thus significantly varies also, and it severely affects the preciseness and the programming performance of the SSI injection.
In aspects of an MLC flash memory cell, a flash memory cell utilizes a low power and is as small as possible to decrease a volume of a related integrated circuit.
Please refer to FIG. 1, which is a diagram of a flash memory cell 100 of the prior art. The flash memory cell 100 is generated according to the MLC technology, and is formed between a drain region 102 and a source region 104 of a semiconductor substrate 106. The nonvolatile memory cell 100 comprises a select gate 108 formed above the semiconductor substrate 106, a first floating gate 110 formed at a first side of the select gate 108 and insulated from the select gate 108 with a first dielectric spacer 112, a second floating gate 114 formed at a second side of the select gate 108 and insulated from the select gate 108 with a second dielectric spacer 116, a first dielectric layer 118 formed on both of the first floating gate 110 and the second floating gate 114, and a control gate 120 formed on the first dielectric layer 118 and being substantially perpendicular to both of the first doping region 102 and the second doping region 104. The first and second floating gates 110 and 114 are utilized for storing programmed bits to implement said MLC technology.
Please refer to FIG. 2, which is a diagram of an exemplary flash memory array 200 comprising a plurality of the flash memory cells 100 shown in FIG. 1 and arranged in rows and columns. In addition to the plurality of the flash memory cells 100, the flash memory array 200 also comprises a first bit source line BLT1 and a second bit source line BLT2, a first word line WL1 and a second word line WL2, a first assist gate AG1 and a second assist gate AG2, a first bit line BL1, a second bit line BL2, a third bit line BL3, a fourth bit line BL4, a first odd transistor 202, a second odd transistor 204, a first even transistor 206, and a second even transistor 208. The plurality of flash memory cells 100 in the flash memory array 200 are classified into a first set of columns of flash memory cells 100 and a second set of columns of flash memory cells 100, as illustrated in FIG. 2, where the first set of columns lies between the bit lines BL1 and BL2, and the second set of columns lies between the bit lines BL3 and BL4. The first bit source line BLT1 is electrically coupled to gates of the first odd transistor 202 and the second odd transistor 204. The second bit source line BLT2 is electrically coupled to gates of the first even transistor 206 and the second even transistor 208. The first bit line BL1 and the third bit line BL3 are respectively electrically coupled to the first odd transistor 202 and the second odd transistor 204, and are respectively electrically coupled to each flash memory cell 100. The second bit line BL2 and the fourth bit line BL4 are respectively electrically coupled to the first even transistor 206 and the second even transistor 208, and are respectively electrically coupled to each flash memory cell 100. The first word line WL1 and the second word line WL2 are respectively electrically coupled to the control gate 120 of each flash memory cell 100 of a different row of rows of flash memory cells 100 in the flash memory array 200. The first assist gate AG1 is electrically coupled to the select gate of each flash memory cell 100 of the first set of columns of flash memory cells 100 in the flash memory array 200. The second assist gate AG2 is electrically coupled to the select gate of each flash memory cell 100 of the second set of columns of flash memory cells 100 in the flash memory array 200.
The flash memory array 200 shown in FIG. 2 is just an exemplary flash memory array utilizing the MLC technology. There are more flash memory arrays having more flash memory cells 100 than in FIG. 2. Therefore, the number of said flash memory cells 100 in said first set of columns of flash memory cells may be more than in the number shown in FIG. 2, as well as the number of said flash memory cells 100 in said second set of columns of flash memory cells 100. Therefore, the number of corresponding odd transistors, even transistors, bit lines, word lines must also be increased accordingly. During programming, the bit source lines and the assist gates directly correspond to column operations of the first and second sets of columns of flash memory cells 100 in an alternative manner for programming the bits stored in the floating gates 110 and 114 of each flash memory cell 100 in the flash memory array 200.